Infineon PSC3
The Infineon PSC3 are Cortex-M33-based microcontrollers suitable for a wide range of secure applications.
The following PSC3 devices are covered by this article:
- PSC3M2/PSC3P2
- PSC3M3/PSC3P3
- PSC3M5/PSC3P5
Flash Banks
PSC3xxE
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| FLASH_NS [1] | 0x22000000 |  |
|
Default | 256 KB |
| FLASH_S [2] | 0x32000000 | |
|
Default | 256 KB |
PSC3xxF
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| FLASH_NS [1] | 0x22000000 | |
|
Default | 512 KB |
| FLASH_S [2] | 0x32000000 | |
|
Default | 512 KB |
Dual Bank Mode
- The devices can be configured to operate in either single-bank or dual-bank mode.
- For PSC3MxG and PSC3PxG devices, the 256 KB flash memory is split into two 128 KB banks in dual-bank mode.
- For PSC3MxF and PSC3PxF devices, the 512 KB flash memory is split into two 256 KB banks in dual-bank mode.
- The alternate bank is accessible at
0x22800000through the non-secure alias and at0x32800000through the secure alias.
Flash programming
To program a device configured for dual-bank mode, the DualBank flash loader must be selected.
The flash loader selection must be appended to the device name.
For example, for the non-secure flash bank, use:
PSC3xxF?BankAddr=0x22000000&Loader=DualBank
instead of:
PSC3xxF
For more information, refer to J-Link Multiple Flashloader.
Flash Layout
PSC3xxE
| Mode | Start address | Size | Description |
|---|---|---|---|
| Dual-bank mode | 0x22000000 | 128 KB | Main bank |
| 0x22800000 | 128 KB | Alternate bank | |
| Single-bank mode | 0x22000000 | 256 KB | Single bank |
PSC3xxF
| Mode | Start address | Size | Description |
|---|---|---|---|
| Dual-bank mode | 0x22000000 | 256 KB | Main bank |
| 0x22800000 | 256 KB | Alternate bank | |
| Single-bank mode | 0x22000000 | 512 KB | Single bank |
Secure Debug
J-Link supports secure debug through Cortex-M33 (CM33) access port authentication. For more information, refer to Infineon PSC3 Secure Debug.
Watchdog Handling
- The device has a watchdog WDT.
- The watchdog reset is disabled when the debugger is connected.
Device Specific Handling
Connect
- PSC3xxF_tm/PSC3xxE_tm: If a normal connect attempt fails, J-Link connects using Test Mode Acquisition sequence, see Test Mode Acquisition
Reset
- The device uses custom reset: Hardware pin reset, RESET(15) must be connected to function.
Attach
- Attach is supported
Test Mode Acquisition
Test mode acquisition is implemented for the PSC3xxF_tm/PSC3xxE_tm device names. If DAP is not accessible, it is possible that the users firmware reconfigured the debug pins to be used as GPIO or disabled the debug port. In this case, J-Link tries to connect to the device in Test mode (TM).