Renesas RX71M
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The Renesas RX71M are microcontrollers from Renesas, which are based on the RXv2 architecture.
Flash Banks
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Internal data flash | 0x00100000 |  |
|
Default | 64 KB |
| Option setting flash | 0x00120040 | |
|
Default | 48 B |
| Internal program flash | 0xFFE00000/0xFFD80000/ 0xFFD00000/0xFFC00000 |
|
|
Default | 2048/2560/ 3072/4096 KB |
Debugger Authentication
If necessary, a debugger authentication via RX ID Code is performed as part of the connect sequence.
See article on Renesas RX cores for further information.
Debug Mode
When using FINE interface, a debug mode is enabled as part of the connect sequence and disabled on debug session close.
Enabling / disabling the debug mode requires writing to the flash.
See article on Renesas RX cores for further information.
Supported debug interfaces
The following debug interfaces are supported:
- JTAG
- FINE