Renesas RX26T
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The Renesas RX26T are microcontrollers from Renesas, which are based on the RXv3 architecture.
Flash Banks
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Internal data flash | 0x100000 |  |
|
Default | 16 KB |
| Internal program flash | 0xFFF80000 | |
|
Default | 128/256/512 KB |
| Option setting flash | 0x00120040 | |
|
Default | 176 B |
Watchdog Handling
- The device has 2 watchdogs: WDTA, IWDTa
- The watchdogs are fed during flash programming
Debugger Authentication
If necessary, a debugger authentication via RX ID Code is performed as part of the connect sequence.
See article on Renesas RX cores for further information.
Debug Mode
When using FINE interface, a debug mode is enabled as part of the connect sequence and disabled on debug session close.
Enabling / disabling the debug mode requires writing to the flash.
See article on Renesas RX cores for further information.
Supported debug interfaces
The following debug interfaces are supported:
- JTAG
- FINE
Evaluation Boards
Tracing
- There is no trace support for this device series