Renesas RA8T2

The Renesas RA8T2 are Cortex-M85 based microcontrollers with optional second Cortex-M33 core.

Flash Banks

Flash bank	Base address	J-Link support	Flasher support	Loader
				Name	Bank size
MRAM (Secure)	0x02000000			Default	up to 1 MB
				RAMLess	up to 1 MB
Configuration (Secure)	0x02C9F020			Default	976 B
OTP (Secure)	0x02E07400			Default	816 B
SiP flash (Secure)	0x08000000			Default	up to 8 MB
MRAM (Non-Secure)	0x12000000			Default	up to 1 MB
				RAMLess	up to 1 MB
Configuration (Non-Secure)	0x12C9F4C0			Default	832 B
OTP (Non-Secure)	0x12E07780			Default	128 B
SiP flash (Non-Secure)	0x18000000			Default	up to 8 MB
External OSPI1 flash CS0	0x70000000			Default	up to 128 MB
External OSPI1 flash CS1	0x78000000			Default	up to 128 MB
External OSPI0 flash CS0	0x80000000			Default	up to 256 MB
External OSPI0 flash CS1	0x90000000			Default	up to 256 MB

Watchdog Handling

• The device has two watchdogs: Watchdog Timer (WDT) and Independent Watchdog Timer (IWDT).
• Both watchdogs are fed during flash programming.

Device Specific Handling

Reset

• The device uses normal Cortex-M reset, no special handling necessary, like described here.

Device Initialization

Device initialization is implemented in the Device Provisioner utility: Renesas_RA8_Initialization.

Evaluation Boards

• MCB-RA8T2
• EK-RA8T2

Example Application

• MCB-RA8T2
• EK-RA8T2

Tracing

This section will provide an overview of the available trace types on this device.

On-chip trace

This device supports so-called on-chip tracing via trace buffer.

For this device this feature works out-of-the-box. Simply select trace buffer as the trace source in your IDE or debug software and you should see trace data recordings when running and halting your application.

Off-chip trace

This device supports so-called off-chip tracing via TPIU.

Off-chip tracing on this device does not work out-of-the-box and requires additional init steps which are explained here.