Renesas RA8E2
The Renesas RA8E2 are Cortex-M85 based microcontrollers.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support | Loaders |
|---|---|---|---|---|
| Code flash option-setting memory (secure) | 0x0300A100 | 384 B |  |
|
| Code flash option-setting memory (non-secure) | 0x1300A180 | 128 B | |
|
| Data flash option-setting memory | 0x27030080 | 720 B | |
|
| Code flash (secure) | 0x02000000 | Up to 2048 KB | |
|
| Code flash (non-secure) | 0x12000000 | Up to 2048 KB | |
|
| Data flash (secure) | 0x27000000 | Up to 12 KB | |
|
| Data flash (non-secure) | 0x37000000 | Up to 12 KB | |
|
- ↑ 1.0 1.1
To use the DualBank loader for CodeFlash, the DUALSEL.BANKMD[2:0] option-setting field must be configured for dual mode. This setting takes effect only after a reset; for all other CodeFlash loaders, the corresponding linear mode must be configured.
The DualBank loader supports bank swapping; however, the user must ensure that the desired bank is mapped to the expected address.
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
Flash programming in OSPI mode is supported for Infineon S28HL512T and S28HS512T only. Other flashes are handled in single/quad mode.
| Bank name | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| External OSPI flash CS0 | 0x80000000 | 256 MB |
|
| External OSPI flash CS1 | 0x90000000 | 256 MB |
|
Data flash specific handling
Data flash in erased state has undefined values, therefore when using J-Flash application, "Skip blank data" and "Perform blank check" options must be disabled in project settings.
Watchdog Handling
- The device has two watchdogs: Watchdog Timer (WDT) and Independent Watchdog Timer (IWDT).
- Both watchdogs are fed during flash programming.
Device Specific Handling
Connect
The connection sequence to RA8 devices is DLM-aware. The general DLM handling is described here and the family-specific handling is documented here.
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
- In case a normal Cortex-M reset fails, a pin reset + CPUWAIT bit is employed as fallback.
Device Initialization
Device initialization is implemented in the Device Provisioner utility: Renesas_RA8_Initialization.
Limitations
Using OEM_PL1 state with J-Flash
Since OEM_PL1 state requires the use of non-secure RAM (0x320D0000-0x320DFFFF), the user has to ensure that the J-Flash project is set up to use this RAM area instead of the secure RAM. By default J-Flash projects are created with secure RAM area (0x220D0000-0x220DFFFF) selected.
Evaluation Boards
- Renesas EK-RA8E2 evaluation board