J-Link PLUS V10
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This page contains the general, mechanical and electrical specifications as well as an overview of supported soft- and hardware features of the SEGGER J-Link PLUS V10.
For information on the general specifications as well as an overview of supported software features refer to J-Link PLUS.
Note:
The J-Link PLUS V10 has been superseded and as such is considered a legacy device.
This device is not eligible for support by SEGGER.
Refer to the J-Link Model Overview for a list of most recent devices by SEGGER.
We recommend to make use of the SEGGER Trade-In-Program to upgrade to the current version of the product.
When new features are added, articles for legacy models may not be updated.
Hardware and Software Features
| Hardware Features | |||||||
| USB 2.0 Full Speed | 
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| USB 2.0 Hi-Speed |
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| JTAG interface |
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| cJTAG interface |
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| SWD interface |
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| SWO interface |
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| SPI interface |
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| QSPI interface | 
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| Microchip ICSP interface |
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| Renesas FINE interface |
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| SiLabs C2 2-wire interface |
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| ETB Trace ARM7/9 |
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| ETB Trace Cortex-M |
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| ETB Trace Cortex-A/R |
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| ETM Trace Cortex-M |
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| VCOM |
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| Memory Stop mode support |
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| Cortex-M Monitor Mode debugging |
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| SWD Multi-Drop |
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| ARM legacy Cores | |||||||
| ARM7 |
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| ARM9 |
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| ARM11 |
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| ARM Cortex Cores | |||||||
| Cortex-A5 |
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| Cortex-A7 |
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| Cortex-A8 |
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| Cortex-A9 |
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| Cortex-A12 |
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| Cortex-A15 |
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| Cortex-A17 |
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| Cortex-A53 |
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| Cortex-A57 |
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| Cortex-A72 |
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| Cortex-M0 |
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| Cortex-M0+ |
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| Cortex-M1 |
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| Cortex-M3 |
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| Cortex-M4 |
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| Cortex-M7 |
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| Cortex-M23 |
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| Cortex-M33 |
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| Cortex-R4 |
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| Cortex-R5 |
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| Cortex-R8 |
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| SC000 (M0 secure) |
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| SC300 (M3 secure) |
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| RISC-V | |||||||
| RV32 |
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| RV64 |
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| Microchip PIC32 | |||||||
| PIC32MX |
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| PIC32MZ |
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| SiLabs 8051 | |||||||
| EFM8 |
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| Renesas RX | |||||||
| RX110 |
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| RX111 |
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| RX210 |
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| RX21A |
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| RX220 |
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| RX610 |
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| RX621 |
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| RX62G |
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| RX62G |
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| RX62N |
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| RX62T |
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| RX630 |
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| RX631 |
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| RX63N |
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| RX63T |
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| RX64M |
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Specifications
| Specification | Value |
|---|---|
| General | |
| Supported OS | Microsoft Windows (x86/x64), Linux (x86/x64/Arm), macOS (x86) |
| Electromagnetic compatibility (EMC) | EN 55022, EN 55024 |
| Operating temperature | +5°C ... +60°C |
| Storage temperature | -20°C ... +65 °C |
| Relative humidity (non-condensing) | Max. 90% rH |
| Mechanical | |
| Size (without cables) | 100mm x 53mm x 27mm |
| Weight (without cables) | 70g |
| Available interfaces | |
| USB interface | USB 2.0 (Hi-Speed); USB Type B |
| Target interface | JTAG 20-pin (14-pin and other adapters available) |
| JTAG/SWD Interface, Electrical | |
| Power supply | USB powered Max. 50mA + Target Supply current. |
| Target interface voltage (VIF) | 1.2V ... 5V |
| Target supply voltage | 5V (derived from USB voltage) |
| Target supply current | Max. 300mA |
| Reset Type | Open drain. Can be pulled low or tristated. |
| Reset low level output voltage (VOL) | VOL <= 10% of VIF |
| For the whole target voltage range (1.2V <= VIF <= 5V) | |
| LOW level input voltage (VIL) | VIL <= 40% of VIF |
| HIGH level input voltage (VIH) | VIH >= 60% of VIF |
| For 1.2V <= VIF <= 3.6V | |
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF |
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF |
| For 3.6 <= VIF <= 5V | |
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF |
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF |
| JTAG/SWD Interface, Timing | |
| Target interface speed | Max. 15 MHz |
| SWO sampling frequency | Max. 30 MHz |
| Data input rise time (Trdi) | Trdi <= 20ns |
| Data input fall time (Tfdi) | Tfdi <= 20ns |
| Data output rise time (Trdo) | Trdo <= 10ns |
| Data output fall time (Tfdo) | Tfdo <= 10ns |
| Clock rise time (Trc) | Trc <= 3ns |
| Clock fall time (Tfc) | Tfc <= 3ns |