device stm32l100rc
if 1
speed 1000
con
sleep 100
w4 0x40023C0C 0x89ABCDEF // Unlock FLASH_PECR
w4 0x40023C0C 0x02030405
w4 0x40023C14 0xFBEAD9C8 // Unlock option byte block
w4 0x40023C14 0x24252627
w4 0x40023C18 0x00000F00 // Clear all error bits in the FLASH_SR
sleep 1
w4 0x1FF80000 0xFF4400BB // Set ROP to Level 1. 0xAA = Level 0; 0xCC = Level 2
sleep 1                  // Format: 0xFF; nRDP; 0x00; RDP
sleep 100                // It is not possible to check the Status register in a commander file,
sleep 100                // therefore we just wait here a fixed amount of time
w4 0x40023C04 0x00040000 // Set OBL_LAUNCH bit
sleep 100                // It is not possible to check the Status register in a commander file,
sleep 100                // therefore we just wait here a fixed amount of time
r                        // Reset device
sleep 100
q